I purchased the first edition of Writing Testbenches: Functional Verification of HDL Models before this site existed.  It was the first good book I found on verification.  By that time I could have written my own book, having learned through trials and tribulations, and living a Transaction-based verification lifestyle at AHA back in 1998.  Nonetheless I appreciated Janick’s efforts.  The first edition concentrated on pure VHDL/Verilog test benches.  The second edition came out after Verisity introduced ‘e’ and System Science’s OpenVera as dedicated verification languages.  I gave the first edition to my coworker Marty and started reading the second, but got caught up in, amongst other things, figuring out how to verify designs in ‘e’.

The ‘e’ language, implemented as the Specman tool by Verisity and later sold to Cadence is still the best verification oriented language I’ve encountered.  It’s ‘aspect-oriented’ programming is exactly what you want for verification.  You establish baseline code then make it super-simple to apply variations to the code for a given test.  This particularly pays off with respect to randomization constraints.  Aspect-oriented code for RTL would be a NIGHTMARE, but is a DREAM for verification.  But alas managers with their hair gel and back-to-school MBA’s said, “we should have one language to poorly do everything and went with System Verilog for both RTL and verification.  (Bergeron would write a book on that three years later).  But SV requires duct-taping the OVM/UVM library on top, with all its complexity, to give you something similar to aspect-oriented.  In the OVM case, a “factory” pattern allows you to replaced specific or all instances of a class with a derived class, modified for your particular test or tests.

In 2022 you are better off reading his subsequent book “Writing Testbenches using System Verilog”, but the second edition is still a strong guide for successful and productive RTL design verification.