VHDL-2008 is a work-related book that describes changes to the VHDL behavioral description language made in the 2008 standard. Electrical engineers who design for FPGA's or ASIC's rely on this language to describe circuits at a very high level. I bought the book when it was released and immediately started reading. Then it started getting a little confusing about the time I realized NONE of the simulation tools I used supported these constructs, nor would any time soon. [Quite a shame as they are very useful]. So back on the shelf it went. I first encountered Ashenden when I read his "Designer's Guide to VHDL" which changed my life. I stopped thinking about logic gates and started thinking about logical behavior. And I started doing things like using records, and overloading operators to make shorter, if not more clear, descriptions. Spring ahead to 2013 when I saw support for 2008 in every tool update. So I dusted off my copy and went to town starting at chapter 2. I flew through the book, which is rare for a technical manual. Without going into gory details, you can now do a lot of things you thought you should have been able to do in the past. Everyone should be using VHDL-2008. About halfway through the first chapter, he starts going into great details about passing generic types into entities, packages, and subprograms. It gets a little dense. I encourage you to power through it as the rest of the topics are pretty straightforward. If you work in my field, read this book.