This is another work-related book, purchased back when I had a great interest in learning verification methodologies. [I still do have an interest but my employer is stuck in the same poorly-scaling text-file approaches they used in 1999]. VMM is a set of methods and techniques promoted by Synopsys. Many people advocated different approaches. Mentor and Cadence eventually settled on something called OVM. This has since "merged" with VMM to become UVM, but basically OVM won the war, retaining the overall framework but adding some features that VMM users couldn't live without. If one was going to split the world into books about the forest and books about trees in the forest, VMM for System Verilog is all about each tree. Page after page of grinding detail about each object/method. Unless you are actively going to use VMM to earn you living, you can skip it. The head author, Janick Bergeron, is a serious guy in the verification world. His original "Writing Testbenches" was the first book I found that demonstrated how to be effective at verification tasks, not just ad hoc. Those books have had several editions, revised as languages and techniques have evolved.